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Intel SoC Design Engineer - BE/Timing in Hillsboro, Oregon

Job Description

Come join Intel's Client Engineering Group, responsible for designing Client SoCs that make up more than half of Intel's annual revenue. We envision the future of computing and design for the next generation of laptops and desktop computers.

We are looking for an SoC (System on Chip) Design Engineer - BE/Timing ready to research, design, develop, and test lead Intel designs as we re-imagine how to build SoCs at Intel and in the semiconductor industry. This role is within Intel's highly-regarded Devices Development Group, headquartered in Portland, Oregon with additional sites in Austin, Texas, and Penang, Malaysia. Our bold purpose as a company is to "create world-changing technology that enriches the lives of every person on earth" and this role is instrumental in furthering our mission to shape the future of technology.

Responsibilities of the role may include, but not be limited to:

  • Drive performance optimization, including co-optimization work with process teams, to create best-in-class designs

  • Physical synthesis, place and Route, and clock tree synthesis with Synopsys or Cadence tools

  • Static timing analysis, constraint understanding, generation, clock stamping, and timing closure

  • Multiple Power Domain analysis using standard Power Formats UPF/CPF

In addition to the qualifications listed below, the ideal candidate will also have/be:

  • Self-motivator with strong problem solving skills

  • Leadership skills with the willingness to mentor junior designers

  • Interpersonal skills

  • Written and verbal communication skills

  • Willingness to work as part of a team and collaborate in a high-paced atmosphere.


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

Candidate must have a Bachelors degree in Electrical/Computer Engineering and 8+ years of experience in: - OR - a Masters degree in Electrical/Computer Engineering and 6+ years of experience in:

Design principles and techniques in SoC and/or VLSI back-end design and/or integration covering 2 or more of the following:

  • Synthesis with Synopsys Design Compiler DCT

  • Static Timing Analysis including Constraint understanding, generation, clock stamping and timing closure

  • DFT, Scan Insertion, and coverage analysis

  • Place and Route

  • Clock tree synthesis

  • Multiple Power Domain Analysis using standard Power Formats UPF/CPF

Preferred Qualifications

10+ years of experience in one or more of the above areas

Inside this Business Group

The Devices Development Group (DDG) is a global organization focused on the development and integration of SOCs, critical IPs including Atom and chipsets that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.