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Intel Principal Engineer - IP Firmware Architect in Hillsboro, Oregon

Job Description

Come and join us! Intel is seeking a Principal Engineer to join the IP Firmware Architecture team within the IP Engineering Group (IPG). IPG develops IPs that enable the creation of Intel products. As an IP Firmware Architect, you will help lead and drive Intel's approach for the co-development and validation of IP hardware and firmware. You will lead the architectural definition of the firmware interfaces for a family of IPs within a technology domain such as I/O, memory, cache coherent fabrics or other technologies. You will be responsible for leading the design and implementation of proof of concept prototypes, tools, and the design of processes necessary for the development & validation of industry leading IPs.

Qualifications

Qualifications for an Ideal Candidate: � Bachelor's degree or higher in Computer Science, Computer Engineering, Electrical Engineering, or equivalent. � 15+ years of industry experience. � Extensive experience in working with and leading cross functional Platform, SoC, and/or IP teams including Architecture, Design, Firmware, and Validation in the development of high-volume production silicon or board-level products. � Extensive experience in the architecture and development of low-level software/firmware requiring direct interaction with hardware. � Experience in the development of processes and tools used for SoC, IP and/or Platform design and validation. � Experience in the design and development of test infrastructure and the associated validation or verification testing. � Significant technical leadership roles in a large firmware project and/or the associated test infrastructure necessary to deliver silicon that has shipped in high volume. � Continued demonstration of SW/FW development skills across various programming languages and development environments. � Strong technical communication skills with proven experience using them in various technical and non-technical scenarios. � Demonstrated ability to work across organizations, geographies, and companies to drive technical direction and collaborate to solve technical issues. � Demonstrated ability to solve complex system level problems involving both technical and non-technical constraints. Additional Preferred Qualifications: � Master's degree or higher preferred. � Experience with programming and debug I/O interfaces such as PCIe. � Experience with programming and debug of memory interfaces such as DDR4. � Experience with programming and debug of cache-coherent SoC fabrics. � Experience with SoC validation and debug including System Verilog development, RTL Simulation environments and SOC emulation environments.

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, California, Folsom;US, California, Santa Clara;US, Massachusetts, Hudson

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter....

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