Intel Principal Engineer - Back-end/Timing in Hillsboro, Oregon
Come join Intel’s Client Engineering Group, responsible for designing Client SOCs that make up more than half of Intel’s annual revenue. We envision the future of computing and design for the next generation of Laptops and desktop computers. We are looking for a Principal Engineer focused on SoC (System on Chip) physical design, ready to research, design, develop, and test lead Intel designs as we reimagine how to build SOCs at Intel and in the semiconductor industry. This is a leadership role requiring the ability to influence within Intel’s highly-regarded Devices Development Group, headquartered in Portland, Oregon with additional sites in Austin, Texas, and Penang, Malaysia. Our bold purpose as a company is to “create world-changing technology that enriches the lives of every person on earth” and this role is instrumental in furthering our mission to shape the future of technology.
Your responsibilities may include, but not be limited to:
Develop and drive project execution and methodology while working with both external and internal tool vendors
Provide technical direction to, and collaborate with, platform and business units
Drive performance optimization, including co-optimization work with process teams, to create best-in-class designs
Expand and standardize design methodologies, especially those related to static timing analysis, cross-clocking domains, and multiple power domain analysis.
The ideal candidate will exhibit behavioral traits that indicate:
Self-motivator with strong problem solving skills.
Strong leadership skills with ability to mentor junior designers.
Excellent interpersonal skills, including written and verbal communication.
Ability to work as part of a team and collaborate in a high-paced atmosphere.
BS or MS in Electrical Engineering, Computer Engineering, or Electrical & Computer Engineering
Minimum 12 years' experience with design principles and techniques in SoC and/or VLSI back-end design and/or integration covering 3 or more of:
Constraint understanding, generation, clock stamping and timing closure
Synthesis with Synopsys Design Compiler DCT
DFT, Scan Insertion, and coverage analysis
Multiple Power Domain Analysis using standard Power Formats UPF/CPF
Place and Route and clock tree synthesis
Static Timing Analysis
- Minimum 15 years' experience in back-end design and/or integration.
Inside this Business Group
The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....
Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter....
- Intel Jobs