Intel Platform Validation Engineer in Hillsboro, Oregon

Job Description

In this position, the successful candidate will be a key member of the Technology Process Development (TPD) team, Integration Testing and Release (ITR) engineering team within TMG with a focus on ensuring the consistency and quality of TPD design collateral used to enable development of SoC designs. This vital position evaluates HIP, block level and SoC level against integration compliance requirements to ensuring that high quality design collateral is delivered to SoC design team enabling them to design and deliver their products as efficiently and quickly as possible.

You will work with IP, methodology, SoC, program managers, customer support and design automation teams on requirements, test scenarios, identified issues and assessment requests to fulfill this mission. Experience will be gained with TPD Hard and Soft IPs including, but not limited to, SerDes, DDR, GPIO, Thermal Sensors, PLLs, DLLs, IDV, Compiled Memories and various mixed-signal designs for leading edge technologies. Development and testing will be done at the IP, block and SoC levels.

Responsibilities include (but not limited to):

  • Interact with kit, methodology and HIP and SoC design teams to identify issues, define test scenarios and develop block and platform test vehicles to ensure high quality platform deliverables

  • Work with process design kits and ASIC design flows to implement automated design configurations using PERL, TCL, etc.

  • Develop and execute IP level integration tests to evaluate hard IP against integration compliance requirements

  • Debug failures in quality checks with IP design teams and coordinating delivery of solutions.

  • Building consensus across multiple vendors to define consistent IP quality metrics.Our challenge is to ensure goal is zero integration issues when using TPD collaterals. If you like variety, want to work at various levels and have a strong drive to learn, this is the position for you.

Behavioral traits:

  • The applicant should have proven ability to clearly communicate with the technical community, customers, as well as management.

  • The candidate should be self-motivated, a team player, results/customer/quality-oriented, and have excellent problem-solving skills.

  • The candidate must be comfortable in short-cycle, multi-project and multi-site/time-zone environment.


Minimum Qualifications:

  • Candidates must have a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or closely related field:

3 to 5 years of experience in:

  • Memory design

  • Low power, high performance design techniques

  • Analog and Mixed-Signal

  • Circuit Design Debug/Characterization (such as Compiled or customer Memories, SerDes, DDR, PLL, DLL, ADC, LDO, etc.)

  • SOC and Mixed-signal CAD/SW development tools (Synopsys, Cadence & Mentor) as well as additional analysis tools such as Excel (for data analysis and indicators),

  • Customer Support and troubleshooting vendor/customer issues.

Preferred Qualifications:

  • Delivering Analog/Memory IP

  • Active participation in cross-functional working groups that drive IP development method and quality improvements.

  • TCL, Perl, and Fractal Crossfire

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth

Other Locations

US, California, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....